Design of Reconfigurable Hardware Architectures for Real-time Applications

access variable addressing mode application-specific bandwidth bit-reversed block buffer butterfly captured CBFP clock cycle co-optimized complex computational configuration constructed CORDIC data scaling delay feedback descriptor design exploration Digital Holographic Imaging digital image sensor digital signal processing embedded system enable evaluated external memory FFT core FPGA functionality global hardware accelerator Hence hybrid floating-point IEEE International illustrated in Figure image reconstruction image sensor implementation input instruction interface latency logic synthesis Mats Gustafsson memory access memory array memory cells memory requirements microscope NFFT OSCI output packets parallel parameters phase phase unwrapping photographic film pipeline FFT pixels port presented Proceedings of IEEE processing cells processing units processor radix-2 real-time reconfigurable architectures Reconfigurable Computing registers reorder resource cells router run-time Scenic shell Section shown in Figure signal processing simulation models specification SQNR stream SystemC Thomas Lenart throughput transform two-dimensional FFT VHDL Viktor Öwall wordlength